As semiconductor processing technology approaches the limits of traditional CMOS scaling, process integration has become increasingly difficult, and has resulted in diminished rates of performance improvement. Consequently, there is currently considerable interest in the art for chip and package stacking solutions, including “system in package” (SiP) and “package on package” (PoP) technologies. Further performance and form factor advantages may be realized through the implementation of 3D integration technologies. Through silicon vias (TSV) are an important key to solutions of this type, since they enable three dimensional stacking and integration of semiconductor devices.